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may 2010 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 fan6753 ? highly integrated green-mode pwm controller fan6753 highly integrated green-mode pwm controller features ? high-voltage startup ? low operating current: 2.7ma ? adaptive decreasing pwm frequency to 22khz ? built-in full-range frequency hopping to reduce emi emission ? fixed pwm frequency: 65khz ? peak-current-mode control ? cycle-by-cycle current limiting ? leading-edge blanking (leb) ? synchronized slope compensation ? internal auto-recovery open-loop protection ? gate output maximum voltage clamp: 18v ? v dd under-voltage lockout (uvlo) ? v dd over-voltage protection (ovp) , auto recovery / latch for option ? internal auto-recovery sense short-circuit protection for option ? constant power limit (full ac input range) ? internal otp sensor with hysteresis ? built-in 5ms soft-start function ? built-in latch pin pull high (> 5.2v) latch function applications general-purpose switch-mode power supplies and flyback power converters, including: ? power adapters ? open-frame smps description the highly integrated fan6753 pwm controller provides several features to enhance the performance of flyback converters. to minimize standby power consumption, a proprietary adaptive green-mode function provides frequency modulation at light-load conditions. to avoid acoustic- noise problems, the minimum pwm frequency is set above 22khz. this green-mode function enables the power supply to meet international power conservation requirements. with the internal high-voltage startup circuitry, the power loss due to bleeding resistors is also eliminated. to further reduce power consumption, fan6753 is manufactured using the bicmos process, which allows an operating current of only 2.7ma. fan6753 integrates a full-range frequency-hopping function internally that helps reduce emi emission of a power supply with minimum line filters. its built-in synchronized slope compensation achieves stable peak-current-mode control. the proprietary internal line compensation ensures constant output power limit over a wide ac input voltage range, from 90v ac to 264v ac . fan6753 provides many protection functions. in addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. pwm output is disabled until v dd drops below the uvlo lower limit, when the controller starts up again. as long as v dd exceeds ~26v, the internal ovp circuit is triggered. available in the 8-pin sop and dip packages. ordering information part number operating temperature range package packing method fan6753my -40 c to +105 c 8-lead, small outline package tape & reel FAN6753NY -40 c to +105 c 8-lead, dual in-line package tube
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 2 fan6753 ? highly integrated green-mode pwm controller marking information figure 1. top mark pin configuration figure 2. pin configuration (top view) pin definitions pin # name description 1 latch for external latch circuit used. when v latchth > 5.2v and after 100s, ic is latched off. 10k ? to gnd is recommended. internal has a sourcing current of 100a (i latch ), 100a 10k ? . the voltage on this pin is 1v (under v latchth =5.2v). 2 fb the signal from the external compensation circuit is fed into this pin. the pwm duty cycle is determined in response to the signal on this pin and the current-sense signal on the sense pin. 3 sense current sense. the sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. 4 gnd ground. 5 gate the totem-pole output driver. soft-driv ing waveform is impl emented for improved emi. 6 v dd power supply. the internal protection ci rcuit disables pwm output as long as v dd exceeds the ovp trigger point. 7 nc no connection. 8 hv for startup, this pin is pulled high to the line input or bulk capacitor via resistors. f: fairchild logo z: plant code x: 1-digit year code y: 1-digit week code tt: 2-digit die run code t: package type (m:sop, n:dip) p: y=green package m: manufacture flow code zxytt 6753 tpm 1 2 3 4 sop & dip 8 7 6 5 latch fb sense gnd hv nc v dd gate
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 3 fan6753 ? highly integrated green-mode pwm controller application diagram figure 3. typical application internal block diagram figure 4. functional block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 4 fan6753 ? highly integrated green-mode pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage (1, 2) 30 v v fb fb pin input voltage -0.3 7.0 v v sense sense pin input voltage -0.3 7.0 v v latch latch pin input voltage -0.3 7.0 v v hv hv pin input voltage 500 v p d power dissipation (t a 50c) 400 mw ja thermal resistance (junction-to-air) 141 c/w t j operating junction temperature -40 +125 c t stg storage temperature range -55 +150 c t l lead temperature (wave soldering or ir, 10 seconds) +260 c esd electrostatic discharge capability human body model, jedec:jesd22-a114 5.5 kv charged device model, jedec:jesd22-c101 1500 v notes : 1. all voltage values, except differential voltages, ar e given with respect to the network ground terminal. 2. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 5 fan6753 ? highly integrated green-mode pwm controller electrical characteristics v dd =15v and t a =25 c unless otherwise noted. symbol parameter conditions min. typ. max. units v dd section v op continuously operating voltage 22 v v dd-on start threshold voltage 14.5 15.5 16.5 v v dd-off minimum operating voltage 8.5 9.5 10.5 v i dd-st startup current v dd-on ? 0.16v 30 a i dd-op operating supply current v dd =15v, gate open 2.7 3.7 ma i dd-olp internal sink current v th-olp +0.1v 30 60 90 a v th-olp i dd-olp off voltage 6.5 7.5 8.0 v v dd-ovp v dd over-voltage protection 25 26 27 v t d-vddovp v dd over-voltage protection debounce time 75 125 200 s hv section i hv supply current drawn from hv pin v ac =90v (v dc =120v), v dd =0v 2.0 3.5 5.0 ma i hv-lc leakage current after startup hv=500v, v dd =v dd-off +1v 1 20 a oscillator section f osc frequency in nominal mode center frequency 62 65 68 khz hopping range 3.7 4.2 4.7 t h - op hopping period 4.4 ms f osc-g green-mode frequency 18 22 26 khz f dv frequency variation vs. v dd deviation v dd =11v to 22v 5 % f dt frequency variation vs. temperature deviation t a =-20 to 85 c 5 % continued on the following page? figure 5. v fb vs. pwm frequency pwm frequency f osc f osc-g v fb-n v fb-g v fb
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 6 fan6753 ? highly integrated green-mode pwm controller electrical characteristics (continued) v dd =15v and t a =25 c unless otherwise noted. symbol parameter conditions min. typ. max. units latch section v latchth latch-off threshold voltage v latchth > 5.2v, after 100s latch off 5.0 5.3 5.6 v t d-latch latch-off de - bounce time v latch < v latchth 40 100 160 s i latch output current from latch pin 92 100 108 a feedback input section a v input voltage to current-sense attenuation 1/4.5 1/4.0 1/3.5 v/v z fb input impedance 4 7 k ? v fb-open output high voltage fb pin open 5.0 5.3 5.6 v v fb-olp fb open-loop trigger level 4.6 4.8 5.0 v t d-olp delay time of fb pin open-loop protection 50 56 62 ms v fb-n green-mode entry fb voltage 2.8 3.0 3.2 v v fb-g green-mode ending fb voltage 2.2 2.4 2.6 v i fb-zdc zero duty-cycle fb current 1.5 ma current-sense section z sense input impedance 12 k ? v sthfl current limit flatten threshold voltage duty>40% 0.87 0.90 0.93 v v sthva current limit valley threshold voltage v sthfl ?v sthva duty=0% 0.30 0.34 0.38 v t pd delay to output 100 200 ns t leb leading-edge blanking time 100 140 180 ns t ss period during soft-startup time startup time 4.3 5.0 5.7 ms gate section dcy max maximum duty cycle 60 65 70 % v gate-l gate low voltage v dd =15v, i o =50ma 1.5 v v gate-h gate high voltage v dd =12v, i o =50ma 8 v t r gate rising time v dd =15v, c l =1nf 150 250 350 ns t f gate falling time v dd =15v, c l =1nf 30 50 90 ns i gate-source gate source current v dd =15v, gate=6v 250 ma v gate-clamp gate output clamping voltage v dd =22v 18 v over-temperature protection section (otp) t otp protection junction temperature (3) +135 c t restart restart junction temperature (4) t otp - 25 c notes : 3. when activated, the output is disabled and the latch is turned off. 4. the threshold temperature for enabling the output again and resetting the latch, after over-temperature protection has been activated.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 7 fan6753 ? highly integrated green-mode pwm controller typical performance characteristics 0 5 10 15 20 25 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) i dd_st ( a) 0 1 2 3 4 5 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) i dd-op (ma) figure 6. startup current (i dd-st ) vs. temperature figure 7. operation supply current (i dd-op ) vs. temperature 13 14 15 16 17 18 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) v dd-on (v) 7 8 9 10 11 12 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) v dd-off (v) figure 8. start threshold voltage (v dd-on ) vs. temperature figure 9. minimum operating voltage (v dd-off ) vs. temperature 0 1 2 3 4 5 6 7 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) i hv (ma) 0 2 4 6 8 10 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) i hv-lc ( a) figure 10. supply current drawn from hv pin (i hv ) vs. temperature figure 11. hv pin leakage current after startup (i h v -lc ) vs. temperature 60 62 64 66 68 70 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) f osc (khz) 62 64 66 68 70 72 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) dcy max (%) figure 12. frequency in normal mode (f osc ) vs. temperature figure 13. maximum duty cycle (dcy max ) vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 8 fan6753 ? highly integrated green-mode pwm controller typical performance characteristics 3 4 5 6 7 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) v fb_olp (v) 48 50 52 54 56 58 60 62 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) tlps (ms) figure 14. fb open-loop trigger level (v fb-olp ) vs. temperature figure 15. delay time of fb pin open-loop protection (t d-olp ) vs. temperature figure 16. output current from latch pin (i latch ) vs. temperature figure 17. latch-off threshold voltage (v latchth ) vs. temperature 25 25.5 26 26.5 27 27.5 28 -40 -30 -15 0 25 50 75 85 100 125 temperature ( ) vdd_ovp (v) figure 18. v dd over-voltage protection (v dd-ovp ) vs. temperature
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 9 fan6753 ? highly integrated green-mode pwm controller functional description startup current for startup, the hv pin is connected to the line input or bulk capacitor through an external diode and resistor, r hv , (1n4007 / 100k ? recommended). typical startup current drawn from the hv pin is 3.5ma and charges the hold-up capacitor through the diode and resistor. when the v dd capacitor level reaches v dd-on , the startup current switches off. at this moment, the v dd capacitor only supplies the fan6753 before the auxiliary winding of the main transformer provides the operating current. for higher than 6kv surge test, r hv of 100k ? or above is recommended. operating current operating current is around 2.7ma. the low operating current enables better efficiency and reduces the requirement of v dd hold-up capacitance. green-mode operation the proprietary green-mode function provides off-time modulation to reduce the switching frequency in light- load and no-load conditions. the on time is limited for better abnormal or brownout protection. v fb , which is derived from the voltage feedback loop, is taken as the reference. once v fb is lower than the threshold voltage, the switching frequency is continuously decreased to the minimum green-mode frequency of around 22khz. current sensing / pwm current limiting peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. the switch current is detected by a sense resistor into the sense pin. the pwm duty cycle is determined by this current-sense signal and v fb , the feedback voltage. when the voltage on the sense pin reaches around v comp =(v fb ?0.6)/4, the switch cycle is terminated immediately. v comp is internally clamped to a variable voltage around 0.9v for output power limit. leading-edge blanking (leb) each time the power mosfet is switched on, a turn-on spike occurs on the sense resistor. to avoid premature termination of the switching pulse, a leading-edge blanking time is built in. during this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 15.5v and 9.5v, respectively. during startup, the hold-up capacitor must be c harged to 15.5v through the startup resistor to enable the ic. the hold-up capacitor continues to supply v dd before the energy can be delivered from auxiliary winding of the main transformer. v dd must not drop below 9.5v during startup. this uvlo hysteresis window ensures that the hold-up capacitor is adequate to supply v dd during startup. gate output / soft driving the bicmos output stage is a fast totem-pole gate driver. cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. the output driver is clamped by an internal 18v zener diode to protect power mosfet transistors against undesirable gate over voltage. a soft driving waveform is implemented to minimize emi. soft-start for many applications, it is necessary to minimize the inrush current at startup. the built-in 5ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot. built-in slope compensation the sensed voltage across the current-sense resistor is used for peak-current-mode cont rol and pulse-by-pulse current limiting. built-in slope compensation improves stability and prevents sub-harmonic oscillation. fan6753 inserts a synchronized, positive-going ramp at every switching cycle. constant output power limit when the sense voltage across sense resistor r s reaches the threshold voltage, around 0.9v, the output gate drive is turned off after a small delay, t pd . this delay introduces an additional current proportional to t pd ? v in / l p . since the delay is nearly constant regardless of the input voltage v in , higher input voltage results in a larger additional current and the output power limit is higher than under low input line voltage. to compensate this variation for a wide ac input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. the power limiter is designed as a positive ramp signal fed to the inverting input of the ocp comparator. this results in a lower current limit at high-line inputs than at low-line inputs. v dd over-voltage protection (ovp) v dd over-voltage protection is built in to prevent damage due to abnormal conditions. if the v dd voltage is over the over-voltage protection voltage (v dd-ovp ) and lasts for t d-vddovp , the pwm pulses are disabled until the v dd voltage drops below the uvlo, then starts again. over-voltage conditions are usually caused by open feedback loops. external latch function (latch pin) the latch pin can be used to control the fan6753 entering latch mode by pulling this pin over 5.2v for 100s. if floating, the latch pin is internally pulled high to 3.5v. it is not recommended to float or short the latch pin to gnd. this pin also includes a test mode to disable the jitter function. latch pin internally sources 100a, so place a resistor in series to gnd. do not let this voltage exceed 5.2v for the fan6753 to function normally.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 10 fan6753 ? highly integrated green-mode pwm controller functional description (continued) limited power control the feedback (fb) voltage increases every time the output of the power supply is shorted or overloaded. if the fb voltage remains higher than a built-in threshold for longer than t d-olp , pwm output is turned off. as pwm output is turned off, v dd begins decreasing. when v dd goes below the turn-off threshold (~9.5v), the controller is totally shut down. v dd is charged up to the turn-on threshold voltage of 15.5v through the startup resistor until pwm out put is restarted. this protection feature continues as long as the overloading condition persists. noise immunity noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuous- conduction mode. slope compensation helps alleviate this problem. good placement and layout practices should be followed. avoiding long pcb traces and component leads, locating compensation and filter components near the fan6753, and increasing the power mos gate resistance also improve performance. over-temperature protection (internal otp) the built-in temperature-sensing circuit shuts down pwm output once the junction temperature exceeds 135c. while pwm output is shut down, v dd gradually drops to the uvlo voltage (around 7.5v). then v dd charges up to the startup threshold voltage of 15.5v through the startup resistor until pwm output is restarted. this ?hiccup? mode protection occurs repeatedly as long as the temperature remains above 130c. the temperature hysteresis window for the otp circuit is 25c.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 11 fan6753 ? highly integrated green-mode pwm controller physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 19. 8-pin small outline package (sop) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 12 fan6753 ? highly integrated green-mode pwm controller physical dimensions 5.08 max 0.33 min 2.54 7.62 0.56 0.355 1.65 1.27 3.683 3.20 3.60 3.00 6.67 6.096 9.83 9.00 7.62 9.957 7.87 0.356 0.20 notes: unless otherwise specified a) this package conforms to jedec ms-001 variation ba b) all dimensions are in millimeters. c) dimensions are exclusive of burrs, mold flash, and tie bar extrusions. d) dimensions and toleranc es per asme y14.5m-1994 8.255 7.61 e) drawing filename and revsion: mkt-n08frev2. (0.56) figure 20. 8-pin dual in-line package (dip) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and condition s, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan6753 ? rev. 1.0.2 13 fan6753 ? highly integrated green-mode pwm controller

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